1. Field of the Invention
The present invention is directed to an improved RAM cell precharge circuit and, more particularly, to an NFET/PFET precharge circuit which minimizes the RAM cell operational voltage range.
2. Description of the Related Art
The past few years have seen a dramatic increase in the speed and power of personal computing systems. Indeed, since general acceptance of personal computer systems in the 1960's, the speed and power of such systems have grown with an almost power law dependence.
Random-Access-Memory (RAM) design is a particular enabling technology for modem day high-speed computer systems and, in the computer industry, has given rise to larger and larger memory capacities allowing larger and more complex application programs to be hosted on desktop or laptop computer systems. However, with the increase in memory capacity on a single chip, with multiple gigabit memories being common, valuable silicon real estate must be conserved from encroachment by support circuitry such as read sense amplifiers.
Specifically, most conventional SRAM circuit designs incorporate 2 bit lines per bit to read the stored digital value from an SRAM storage cell. Using 2-bit lines is done so that the read circuitry which evaluates the state of the storage cell can be implemented using differential sensing techniques such that the read access times of the SRAM can be minimized. When implementing an SRAM read sense amp using differential bit lines, a circuit designer must take into account the voltage range to which the bit lines will charge up to. The smaller the voltage range, the easier it becomes to design and construct a high performance, efficient differential bit line sense amplifier.
A typical prior art-type SRAM storage cell, sense amp, and precharge circuitry is depicted in semi-schematic block diagram form in FIG. 1. Basically, a RAM storage cell 10 is configured to output its pre-programmed state on differential bit lines 12 and 14 which are precharged by pre-charge NFET transistors 16 and 18, coupled between a voltage supply and the bit lines 12 and 14, respectively. The RAM cell 10 outputs its pre-programmed state differentially, by outputting the digital state value Q and its logical inverse Q onto the bit lines. This differential signal is read by a sense amp 20 which outputs either a logical ONE or ZERO in response to the "sense" of the differential signal.
During a precharge cycle, the NFET precharge transistor 16 and 18 are driven by a buffer 22, traditionally a large PFET/NFET inverter circuit, in response to an active-low PRECHG signal issued by peripheral SRAM circuitry. In conventional fashion, the 2-bit lines 12 and 14 are precharged by the pre-charge NFETs to a value of about the supply voltage minus the threshold voltage of the NFET, V.sub.DD- V.sub.TN,after the pre-charge transistors are turned on and the transistor response has time to settle. After the precharge cycle is complete, the SRAM storage element 10 is allowed to drive the bit lines. One of the bit lines will be driven to a logical high (a relatively simple condition since each bit line is already charged) while the other will be driven to a logical low. As the bit lines start diverging in their respective voltage values, the sense amp 20 "senses" the difference between the voltage values on the bit lines and drives its output either high or low depending on the "sense" of the difference.
For high speed response, the design of this differential sense amplifier needs to be optimized as a function of particular differential voltage ranges. For example, the optimum circuit implementation of a differential sense amplifier operating at an initial bit line precharge voltage of approximately 2.6 volts would be quite different from the optimum circuit design of a differential sense amplifier that was optimized for an initial bit line voltage of about 2 volts. If the design were required to account for this difference in initial operational voltages of the bit lines, the design would be far less efficient due to the need to either sacrifice speed and/or operate at a higher power level to accommodate the greater voltage swing.
The source of voltage swing irregularities will become apparent when considering well known time response characteristic curves depicted in FIG. 2. In well understood fashion, when the NFET pre-charge transistors 16 and 18 are turned on by an appropriate voltage signal from the buffer 22, the bit lines 12 and 14 initially charge to an intermediate voltage level very quickly. For example, for a circuit coupled to an approximately 3.3 volt supply, the NFET pre-charge transistor 16 and 18 will rapidly charge the bit lines 12 and 14 to a value of approximately 2.0 volts. The initial voltage response is rapid and substantially linear up to the about 2.0 volt level, at which time the voltage response rolls-off and increases more slowly. This slow increase in bit line voltage continues until the bit lines 12 and 14 are fully pre-charged to a final level approximately equal to the supply voltage minus the threshold voltage of the NFET, V.sub.TN. In the illustration of FIG. 2, the first characteristic curve represents a turn-on signal applied to an exemplary pre-charge transistor. The second characteristic curve represents the high-to-low and low-to-high response characteristics of a typical transistor, and graphically depicts the finite time required to achieve V.sub.out =V.sub.DD -V.sub.TN.
While inconvenient, the major difficulty with finite response occurs during burst reads of the RAM cell 10 where the pre-charge transistors 16 and 18 are being switched on and off at a relatively high rate whose period exceeds the characteristic T.sub.LH of the transistors. In these situations, the pre-charge transistors 16 and 18 are not given enough time to pull the bit lines 12 and 14 up to the full supply rail. The time-dependent roll-off portion of their response characteristics are truncated and the transistors are only able to effectively operate in the early-turn-on portions of their operational regimes, causing the bit lines 12 and 14 to pre-charge to levels of only approximately 2.0 volts. This condition will be evident from examination of the third and fourth characteristic curves of FIG. 2, which depict a high-rate turn-on input pulse train and the corresponding output characteristic curves. With a signal rate greater than T.sub.L, the output response is truncated to a degree where the maximum output voltage is less than the supply rail by some characteristic value .DELTA.V. Thus, the sense amp 20 must also be configured to operate at initial voltage levels of 2.0 volts, as well as initial voltage levels of 2.6 volts. As can be appreciated, such wide input voltage range of the sense amp 20 thus degrades performance.
Thus, what is needed is precharge circuitry that provides a narrower input voltage range for a read sense amplifier of RAM cells so as to improve performance.